supertex inc. supertex inc. www.supertex.com hv2705hv2706 doc.# dsfp-hv2705_hv2706b051512 features ? hvcmos technology for high performance ? integrated bleed resistors on the outputs ? 16-channel high voltage analog switch ? 3.3v input logic level compatible ? 20mhz data shift clock frequency ? very low quiescent power dissipation (-10a) ? low parasitic capacitance ? dc to 50mhz small signal frequency response ? -60db typical off-isolation at 5.0mhz ? cmos logic circuitry for low power ? low harmonic distortion ? cascadable serial data register with latches ? flexible operating supply voltages applications ? medical ultrasound imaging ? ndt metal law detection ? piezoelectric transducer drivers ? optical mems modules general description the supertex hv2705 and hv2706 are low charge injection, 16-channel, high voltage analog switch integrated circuits (ics) with bleed resistors. the devices can be used in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging and piezoelectric transducer drivers. the bleed resistors eliminate voltage build-up on capacitive loads such as piezoelectric transducers. the hv2706 has a different pin coniguration than the hv2705. input data are shifted into a 16-bit shift register that can then be retained in a 16-bit latch. to reduce any possible clock feed-through noise, the latch enable bar should be left high until all bits are clocked in. data are clocked in during the rising edge of the clock. using hvcmos technology, this device combines high voltage bilateral dmos switches and low power cmos logic to provide eficient control of high voltage analog signals. the device is suitable for various combinations of high voltage supplies, e.g., v pp /v nn : +40v/-160v, +100v/-100v, and +160v/-40v. block diagram low harmonic distortion, 16-channel, high voltage, analog switches with bleed resistors dle clr latches level shifters output switches sw0 sw1 sw2 sw14 sw15 16-bit shift register rgnd vpp vnn clr le vdd gnd dle clr dle clr dle clr dle clr dout clk din downloaded from: http:///
2 supertex inc. www.supertex.com hv2705hv2706 doc.# dsfp-hv2705_hv2706b051512 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. parameter value v dd logic supply -0.5v to +7.0v v pp -v nn differential supply 220v v pp positive supply -0.5v to v nn +200v v nn negative supply +0.5v to -200v logic input voltage -0.5v to v dd +0.3v analog signal range v nn to v pp peak analog signal current/channel 3.0a storage temperature -65c to 150c power dissipation: 48-lead lqfp (fg) 1.0w sym parameter value v dd logic power supply voltage 3.0v to 5.5v v pp positive high voltage supply +40v to v nn +200v v nn negative high voltage supply -40v to -160v v ih high level input voltage 0.9v dd to v dd v il low level input voltage 0v to 0.1v dd v sig analog signal voltage peak-to-peak v nn +10v to v pp -10v t a operating free air temperature 0c to 70c recommended operating conditionsnotes: 1. power up/down sequence is arbitrary except gnd must be powered-up irst and powered-down last. 2. v sig must be within v nn and v pp or loating during power up/down transition. 3. rise and fall times of power supplies v dd , v pp , and v nn should not be less than 1.0msec. product marking pin coniguration 48-lead lqfp (fg) (top view) 1 48 yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = green packaging *may be part of top marking top marking bottom marking yyw w hv2705fglllllllll cccccccc aaa 48-lead lqfp (fg) package may or may not include the following marks: si or yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = green packaging *may be part of top marking top marking bottom marking yyw w hv2706fglllllllll cccccccc aaa 48-lead lqfp (fg) package may or may not include the following marks: si or -g indicates package is rohs compliant (green). ordering information / availability part number package option packing hv2705fg-g 48-lead lqfp 250/tray hv2705fg-g m931 48-lead lqfp 1000/reel HV2706FG-G 48-lead lqfp 250/tray HV2706FG-G m931 48-lead lqfp 1000/reel typical thermal resistance package ja 48-lead lqfp 52 o c/w downloaded from: http:///
3 supertex inc. www.supertex.com hv2705hv2706 doc.# dsfp-hv2705_hv2706b051512 sym parameter 0c +25c +70c units conditions min max min typ max min max r ons small signal switch on-resistance - 30 - 26 38 - 48 ? i sig = 5.0ma v pp = +40v v nn = -160v - 25 - 22 27 - 32 i sig = 200ma - 25 - 22 27 - 30 i sig = 5.0ma v pp = +100v v nn = -100v - 18 - 18 24 - 27 i sig = 200ma - 23 - 20 25 - 30 i sig = 5.0ma v pp = +160v v nn = -40v - 22 - 16 25 - 27 i sig = 200ma ?r ons small signal switchon-resistance matching - 20 - 5.0 20 - 20 % i sig = 5.0ma, v pp = +100v, v nn = -100v r onl large signal switchon-resistance - - - 15 - - - ? v sig = v pp -10v, i sig = 1.0a r int value of output bleed resistor - - 20 35 50 - - k? output switch to rgndi rint = 0.5ma i sol switch off leakage per switch* - 5.0 - 1.0 10 - 15 a v sig = v pp -10v and v nn +10v v os dc offset switch off* - 300 - 100 300 - 300 mv no load dc offset switch on* - 500 - 100 500 - 500 mv i ppq quiescent v pp supply current - - - 10 50 - - a all switches off i nnq quiescent v nn supply current - - - -10 -50 - - a all switches off i ppq quiescent v pp supply current - - - 10 50 - - a all switches on, i sw = 5.0ma i nnq quiescent v nn supply current - - - -10 -50 - - a all switches on, i sw = 5.0ma i sw switch output peak current - 3.0 - 3.0 2.0 - 2.0 a v sig duty cycle < 0.1% f sw output switching frequency - - - - 50 - - khz duty cycle = 50% i pp average v pp supply current - 6.5 - - 7.0 - 8.0 ma v pp = +40v v nn = -160v all output switches are turning on and off at 50khz with no load. v pp = +100v v nn = -100v - 4.0 - - 5.5 - 5.5 v pp = +160v v nn = -40v - 4.0 - - 5.0 - 5.5 i nn average v nn supply current - 6.5 - - 7.0 - 8.0 ma v pp = +40v v nn = -160v v pp = +100v v nn = -100v - 4.0 - - 5.0 - 5.5 v pp = +160v v nn = -40v - 4.0 - - 5.0 - 5.5 i dd average v dd supply current - 4.0 - - 4.0 - 4.0 ma f clk = 5.0mhz, v dd = 5.0v i ddq quiescent v dd supply current - 10 - - 10 - 10 a all logic inputs are static i sor data out source current 0.45 - 0.45 0.70 - 0.40 - ma v out = v dd -0.7v i sink data out sink current 0.45 - 0.45 0.70 - 0.40 - ma v out = 0.7v c in logic input capacitance - 10 - - 10 - 10 pf --- dc electrical characteristics(over recommended operating conditions unless otherwise noted) * see test circuits on page 5 downloaded from: http:///
4 supertex inc. www.supertex.com hv2705hv2706 doc.# dsfp-hv2705_hv2706b051512 ac electrical characteristics (over recommended operating conditions, v dd = 5.0v, t r = t f 5.0ns, 50% duty cycle, c load = 20pf, unless otherwise noted) sym parameter 0c +25c +70c units conditions min max min typ max min max t sd set up time before le rises 25 - 25 - - 25 - ns --- t wle time width of le 56 - - 56 - 56 - ns v dd = 3.0v 12 - - 12 - 12 - v dd = 5.0v t do clock delay time to data out 50 100 50 78 100 50 100 ns v dd = 3.0v 15 40 15 30 40 15 40 v dd = 5.0v t wclr time width of clr 55 - 55 - - 55 - ns --- t su set up time data to clock 21 - - 21 - 21 - ns v dd = 3.0v 7.0 - - 7.0 - 7.0 - v dd = 5.0v t h hold time data from clock 2.0 - 2.0 - - 2.0 - ns v dd = 3.0 or 5.0v f clk clock frequency - 8.0 - - 8.0 - 8.0 mhz v dd = 3.0v - 20 - - 20 - 20 v dd = 5.0v t r ,t f clock rise and fall times - 50 - - 50 - 50 ns ---- t on turn on time* - 5.0 - - 5.0 - 5.0 s v sig = v pp -10v, r load = 10k? t off turn off time* - 5.0 - - 5.0 - 5.0 s v sig = v pp -10v, r load = 10k? dv/dt maximum v sig slew rate - 20 - - 20 - 20 v/ns v pp = +40v, v nn = -160v - 20 - - 20 - 20 v pp = +100v, v nn = -100v - 20 - - 20 - 20 v pp = +160v, v nn = -40v k o off isolation* -30 - -30 -33 - -30 - db f = 5.0mhz, 1k?//15pf load -58 - -58 - - -58 - f = 5.0mhz, 50? load k cr switch crosstalk* -60 - -60 -70 - -60 - db f = 5.0mhz, 50? load i id output switch isolation diode current - 300 - - 300 - 300 ma 300ns pulse width,2.0% duty cycle c sg(off) off capacitance sw to gnd - 15 - 10 15 - 15 pf 0v, f = 1.0mhz c sg(on) on capacitance sw to gnd - 18 - 13 18 - 18 pf 0v, f = 1.0mhz +v spk output voltage spike* - - - - 150 - - mv v pp = +40v, v nn = -160v, r load = 50? -v spk +v spk - - - - 150 - - v pp = +100v, v nn = -100v, r load = 50? -v spk +v spk - - - - 150 - - v pp = +160v, v nn = -40v, r load = 50? -v spk qc charge injection* - - - 820 - - - pc v pp = +40v, v nn = -160v, v sig = 0v - - - 600 - - - v pp = +100v, v nn = -100v, v sig = 0v - - - 350 - - - v pp = +160v, v nn = -40v, v sig = 0v * see test circuits on page 5 downloaded from: http:///
5 supertex inc. www.supertex.com hv2705hv2706 doc.# dsfp-hv2705_hv2706b051512 hv2705/hv2706 test circuits dc offset switch on/off v pp 5v v nn vpp vnn vdd gnd v out t on /t off test circuit 5v gnd v pp -10v v out output switch isolation diode current i id 5v gnd v nn v sig switch crosstalk v in = 10v p-p @5mhz nc 5v gnd 50 output voltage spike 5v gnd v out 1k r load 50 +v spk Cv spk off isolation k o = 20log v out v in v in = 10v p-p @5mhz 5v gnd v out 50 r load r load 10k v pp v nn vpp vnn vdd v pp v nn vpp vnn vdd v pp v nn vpp vnn vdd v pp v nn vpp vnn vdd v pp v nn vpp vnn vdd k cr = 20log v out v in v pp -10v switch off leakage per switch (for hv2705 only) rgnd open q = 1000pf x v out charge injection 5v gnd v pp v nn vpp vnn vdd v pp 5v v nn vpp vnn vdd open i sol gnd v out v out 1000pf rgnd rgnd rgnd rgnd rgnd rgnd rgnd v sig downloaded from: http:///
6 supertex inc. www.supertex.com hv2705hv2706 doc.# dsfp-hv2705_hv2706b051512 logic function table notes: 1. the 16 switches operate independently. 2. serial data is clocked in on the l to h transition of the clk. 3. all 16 switches go to a state retaining their latched condition at the rising edge of le. when le is low the shift registers data low through the latch. 4. d out is high when data in the shift register 15 is high. 5. shift registers clocking has no effect on the switch states if le is high. 6. the clr clear input overrides all other inputs. logic timing waveforms data in di n le clock data out dout off on clr v out (typ) 50 % 50 % 50 % 50 % t wle t sd 50 % 50 % t su t h t off 50 % t do t on t wcl d n - 1 d n d n + 1 50 % 50 % 90 % 10 % d0 d1 ... d7 d8 ... d15 le clr sw0 sw1 ... sw7 sw8 ... sw15 l - ... - - ... - l l off - ... - - ... - h - - - - l l on - - - - - l - - - l l - off - - - - h - - - l l - on - - - - - - - - l l - - - - - - - - - - l l - - - - - - - l - - l l - - off - - - - h - - l l - - on - - - - - l - l l - - - off - - - - h - l l - - - on - - - - - - l l - - - - - - - - - - l l - - - - - - - - - - l l - - - - - - - - - - l l - - - - - - - - - l l l - - - - off - - - - h l l - - - - on x x x x x x x h l hold previous state x x x x x x x x h all switches off downloaded from: http:///
7 supertex inc. www.supertex.com hv2705hv2706 doc.# dsfp-hv2705_hv2706b051512 hv2705 pin description 48-lead lqfp (fg) pin # function 1 nc 2 nc 3 sw4b 4 sw4a 5 sw3b 6 sw3a 7 sw2b 8 sw2a 9 sw1b 10 sw1a 11 sw0b 12 sw0a pin # function 13 vnn 14 nc 15 vpp 16 nc 17 gnd 18 vdd 19 din 20 clk 21 le 22 clr 23 dout 24 rgnd pin # function 25 sw15b 26 sw15a 27 sw14b 28 sw14a 29 sw13b 30 sw13a 31 sw12b 32 sw12a 33 sw11b 34 sw11a 35 nc 36 nc pin # function 37 sw10b 38 sw10a 39 sw9b 40 sw9a 41 sw8b 42 sw8a 43 sw7b 44 sw7a 45 sw6b 46 sw6a 47 sw5b 48 sw5a hv2706 pin description 48-lead lqfp (fg) pin # function 1 nc 2 nc 3 sw4b 4 sw4a 5 sw3b 6 sw3a 7 sw2b 8 sw2a 9 sw1b 10 sw1a 11 sw0b 12 sw0a pin # function 13 vnn 14 nc 15 vpp 16 nc 17 gnd, rgnd 18 vdd 19 din 20 clk 21 le 22 clr 23 dout 24 nc pin # function 25 sw15b 26 sw15a 27 sw14b 28 sw14a 29 sw13b 30 sw13a 31 sw12b 32 sw12a 33 sw11b 34 sw11a 35 nc 36 nc pin # function 37 sw10b 38 sw10a 39 sw9b 40 sw9a 41 sw8b 42 sw8a 43 sw7b 44 sw7a 45 sw6b 46 sw6a 47 sw5b 48 sw5a downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. supertex inc . does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//www .supertex.com) ?2012 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www.supertex.co m 8 (the package drawing(s) in this data sheet may not relect the most current speciications. for the latest package outline information go to http://www.supertex.com/packaging.html .) hv2705hv2706 doc.# dsfp-hv2705_hv2706b051512 48-lead lqfp package outline (fg) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch symbol a a1 a2 b d d1 e e1 e l l1 l2 dimension (mm) min 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80* 0.50 bsc 0.45 1.00 ref 0.25 bsc 0 o nom - - 1.40 0.22 9.00 7.00 9.00 7.00 0.60 3.5 o max 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* 0.75 7 o jedec registration ms-026, variation bbc, issue d, jan. 2001. * this dimension is not speciied in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-48lqfpfg version, d041309. 1 seating plane gauge plane l l1 l2 vi ew b view b seating plane top view d d1 e e1 b e side view a2 a a1 note 1 (index area d1/4 x e1/4) 48 note: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. downloaded from: http:///
|
